This application claims the priority benefit of Taiwan application serial no. 90109368, filed Apr. 19, 2001.
1. Field of Invention
This invention relates to a fabrication method for metal interconnects. More particularly, the present invention relates to a fabrication method for a dual damascene structure.
2. Description of Related Art
In the semiconductor industry, to increase the operating speed of a device is an important goal that is constantly being pursued. It is also a major element being demanded by the consumer. In the current speedy development of integrated circuits, the determining factors affecting the operating speed include the resistance of the conductive line and the degree of parasitic capacitance of the dielectric layer. Reducing the resistance of the conductive line can be achieved by selecting low resistance metal material, whereas reducing the parasitic capacitance of the dielectric layer can be achieved by selecting low dielectric constant dielectric material for the insulation layer formed between the multi-level metal interconnects.
The manufacturing for typical metal interconnects includes forming a metal plug in the dielectric layer, followed by forming an aluminum conductive line on the substrate to connect with the metal plug. Dual damascene is a highly reliable and low cost technique for the fabrication of metal lines. Furthermore, the material used for the metal interconnects is not a factor to the limitations in metal etching. The dual damascene technique is thus a popular technique to use in the manufacturing of copper conductive lines to reduce the resistance of the conductive lines and to increase the speed and quality of the integrated-circuit device. As the device becomes more highly integrated, low dielectric constant dielectric layer is used for the manufacturing of the dual damascene structure, which becomes one of the approach in the manufacturing of metal interconnects in the semiconductor industry.
The manufacturing of a dual damascene structure according to the prior art basically includes forming a dielectric layer on a substrate, followed by forming a dual damascene opening in the dielectric layer. Metal copper further fills the dual damascene opening. After this, chemical mechanical polishing is conducted for planarization. Chemical mechanical polishing is used in the back end of line of the above process. However, it is a common knowledge that chemical mechanical polishing would lead to problems including scratch marks remaining on the planarized surface, rip off, particle residue, dishing, erosion, oxide layer generated on the copper surface and diffusion of copper ions in the washing process subsequent to the chemical mechanical polishing process. The defects resulted from the chemical mechanical polishing process would also lead to a lower yield and a reduction in reliability.
The present invention provides a fabrication method for a dual damascene structure, wherein the application of chemical mechanical polishing can be avoided.
The present invention provides a fabrication method for a dual damascene structure. A barrier layer is formed on a semiconductor structure that already comprises a dual damascene opening, wherein the barrier layer covers the dual damascene opening. A seed layer is formed on the barrier layer, covering the surface of the barrier layer. A sacrificial layer is then formed on the seed layer, filling the dual damascene opening. Using the seed layer as an etch-stop layer, the sacrificial layer is etched back. The exposed seed layer is then removed, followed by completely removing the sacrificial layer. Plating is further performed to form a metal layer in the dual damascene opening, filling the dual damascene opening and completing the fabrication of a dual damascene structure. Since the dual damascene structure is manufactured with etching and filling steps described above, there is no need to use any CMP process for making the dual damascene structure. Thus, this prevents the defect problem induced by adopting the CMP process.
The invention provides a fabrication for a dual damascene of the semiconductor back-end of line manufacturing, wherein the application of chemical mechanical polishing is avoided by using a sacrificial layer. This method is also applicable for the back-end of line interconnect manufacturing. Since the common approach in using copper as interconnect requires the application of chemical mechanical polishing for planaization, the problems resulted from chemical mechanical polishing is inevitable. Problems of such include scratch marks remaining on the planarized surface, rip off, particle residue, dishing, erosion, oxide layer generated on the copper surface and diffusion of copper ions in the washing process subsequent to chemical mechanical polishing. The present invention, therefore, avoids the application of chemical mechanical polishing to prevent the above problems. Other potential problems that are resulted from the application of chemical mechanical polishing can also be avoided to increase the yield and to achieve the desired reliability of the product.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.